1. Field of the Invention
Generally, the present disclosure relates to the manufacture of sophisticated semiconductor devices, and, more specifically, to various methods of forming a high quality interfacial layer on semiconductor devices by performing a low temperature atomic layer deposition (ALD) process.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout. Metal oxide field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. A FET (whether an NFET or a PFET) is a device that typically includes a source region, a drain region, a channel region that separates the source region and the drain region, and a gate electrode positioned above the channel region. A gate insulation layer is positioned between the gate electrode and the channel region. Electrical contacts are made to the source and drain regions, and current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For example, for an NFET device, if there is a zero voltage applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when a voltage above the threshold voltage of the device is applied to the gate electrode, the channel region becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. Traditionally, FETs have been substantially planar devices, but similar principles of operation apply to more three-dimensional FET structures, devices that are typically referred to as FinFETs.
For many early device technology generations, the gate structures of most transistor elements have been comprised of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode, i.e., so-called SiON/Poly-Si-Gate technology devices. Historically, the channel length of SiON/Poly-Si-Gate transistor devices was reduced to increase the electrical performance characteristics of the transistors, e.g., to improve the drive current capability of the device and to increase its switching speed. However, with these traditional SiON/Poly-Si-Gate transistor devices, the reduction in channel length reached a limit where undesirable so-called short channel effects caused a decrease in device performance, e.g., an increase in off-state leakage currents. Thus, many newer generation devices employ gate structures comprised of alternative materials in an effort to avoid such short channel effects that were associated with the use of SiON/Poly-Si-Gate transistor devices with very small channel lengths. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 14-32 nm, gate structures having a so-called high-k dielectric/metal gate (HK/MG) configuration have been shown to provide significantly enhanced operational characteristics over the traditional SiON/Poly-Si-Gate transistor devices.
Depending on the specific overall device requirements, several different high-k materials—i.e., materials having a dielectric constant, or k-value, of approximately 10 or greater—have been used with varying degrees of success for the gate insulation layer in HK/MG gate structures. For example, in some transistor element designs, a high-k gate insulation layer, which may include tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicates (HfSiOx) and the like, was formed by depositing the high-k material on the substrate. Thereafter, one or more non-polysilicon metal gate electrode materials—i.e., a metal gate stack—was used in HK/MG configurations so as to control the work function of the transistor. These metal gate electrode materials may include, for example, one or more layers of titanium (Ti), titanium nitride (TiN), titanium-aluminum (TiAl), aluminum (Al), aluminum nitride (AlN), tantalum (Ta), tantalum nitride (TaN), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), tantalum silicide (TaSi) and the like. Silicon-based gate electrode materials could not be used with such high-k gate insulation layers because the resulting transistors exhibited a threshold voltage level that was too high, primarily due to a degradation in the charge carrying capability of the channel.
Additionally, in many cases, modern integrated circuit products contain different regions where the various transistor devices have interfacial insulation layers with different thicknesses. The fact that the products have these different regions with different layer thicknesses can add to processing complexity. FIGS. 1A-1D depict one illustrative prior art process flow that will be referenced for purposes of disclosing at least some of the problems associated with manufacturing such a prior art product.
As shown in FIG. 1A, the product 10 is formed above a semiconducting substrate 12 wherein illustrative isolation regions 14 have been formed in the substrate 12 to define active regions where a plurality of NFET and PFET devices will be formed. In this example, the substrate has Regions A and B, where the transistor devices in Region A of the substrate 12 will have a thicker interfacial layer than the transistor device in Region B. At the point of fabrication depicted in FIG. 1A, illustrative silicon/germanium regions 16 have been formed in the substrate 12 using traditional techniques. In general, the silicon/germanium regions 16 are formed for the PFET devices because it enhances the mobility of charge carriers in the PFET devices, i.e., holes. The silicon/germanium regions 16 are formed using techniques well known to those skilled in the art.
FIG. 1B depicts the product 10 after various process operations, schematically depicted by the arrows 18, are performed to initially form and thereafter treat an illustrative silicon dioxide interfacial layer 20 across the entire substrate 12, including Regions A and B. The first part of the processes represented by the arrows 18 involves performing a chemical vapor deposition (CVD) process at a relatively high temperature, e.g., 600-800° C., to initially form the silicon dioxide interfacial layer 20. The silicon dioxide interfacial layer 20 is typically formed to a thickness 20T which corresponds to the desired thickness of the final interfacial layer in Region A, i.e., the region with devices requiring the thicker interfacial layer. For example, in one illustrative embodiment, the thickness 20T may fall within the range of about 3-4 nm. Unfortunately, performing this high temperature CVD process to form the silicon dioxide interfacial layer 20 causes some out-diffusion of germanium in the silicon/germanium regions 16 of the PFET devices. This out-diffusion of germanium results in the formation of germanium oxide (not shown) at the interface 22 between the silicon dioxide interfacial layer 20 and the silicon/germanium region 16. Unfortunately, germanium oxide is relatively unstable and is not a desirable material for an interfacial layer on a modern integrated circuit product because of the high density of defects that act as charge traps, which degrades the reliability of the PFET devices.
In an effort to eliminate some of the defects in the silicon dioxide interfacial layer 20, the second part of the process operations 18 involves performing a decoupled plasma oxidation process to densify the silicon dioxide interfacial layer 20. In one illustrative embodiment, this plasma oxidation process may be performed at a temperature of about 100-800° C. for a duration of about 5-300 seconds. After the plasma oxidation process is completed, the final part of the schematically depicted process operations 18 involves performing a rapid thermal anneal process on the product 10. In one illustrative embodiment, the rapid thermal anneal process may be performed at a temperature of about 500-1100° C. for a duration of about 5-300 seconds.
FIG. 1C depicts the product 10 after several process operations were performed. First, a patterned mask layer 24 was formed that masks Region A while leaving Region B exposed for further processing. Thereafter, the portion of the silicon dioxide interfacial layer 20 above the Region B was removed by performing an etching or stripping process, typically a wet etching process. Unfortunately, the surface of the silicon/germanium layer 16 for the PFET device in Region B has an undesirable roughness, which can lead to problems such as undesirable and unpredictable shifts in the threshold voltage of the affected PFET device and higher within-wafer variations in the threshold voltages of the devices formed on the substrate 12. The removal of the silicon dioxide interfacial layer 20 also causes excessive loss of the underlying silicon/germanium region 16. That is, as depicted, the thickness 16X of the silicon/germanium region 16 is less than the original thickness 16T of the silicon/germanium material 16.
FIG. 1D depicts the product 10 after several process operation have been performed. First, the silicon dioxide interfacial layer 20 was removed from above the exposed Region B to thereby expose the silicon/germanium region 16. Thereafter, a second silicon dioxide interfacial layer 26 was formed above the devices in Region B. In one illustrative embodiment, the second silicon dioxide interfacial layer 26 was formed by performing a chemical based deposition process and it may have a thickness of about 1 nm. Thereafter, a nitridation process is performed on the second silicon dioxide interfacial layer 26 whereby nitrogen is incorporated into the second silicon dioxide interfacial layer 26. After the nitridation process is performed, a RTO (rapid thermal oxidation) process is performed to grow a layer of silicon dioxide that is about 2-4 nm thick. At the point of fabrication depicted in FIG. 1D, the patterned mask layer 24 is removed and traditional manufacturing operations are performed to fabricate semiconductor devices, e.g., FinFET devices and/or planar transistor devices, above the Regions A and B.
The present disclosure is directed to various methods of forming a high quality interfacial layer on semiconductor devices by performing a low temperature atomic layer deposition (ALD) process that may avoid, or at least reduce, the effects of one or more of the problems identified above.